1. Field of the Invention
The present invention relates generally to a system and method for designing integrated circuits fabricated by a semiconductor manufacturing process and, more particularly, to a system and method for integrated circuit layout partition and extraction for independent layout processing used in designing integrated circuits to enhance manufacturability and, hence, yield of a semiconductor fabrication process used to produce the integrated circuits.
2. References
U.S. Pat. No. 5,858,580
U.S. Pat. No. 6,505,327 B2
U.S. Pat. No. 6,560,766 B2
U.S. Pat. No. 6,807,661 B2
U.S. Pat. No. 6,813,758 B2
U.S. Published Patent Application 20020152454
3. Description of the Prior Art
The semiconductor manufacturing industry is continually evolving semiconductor device designs and fabrication processes and developing new processes to produce smaller and smaller geometries of the designs being manufactured, because smaller semiconductor devices typically consume less power, generate less heat, and operate at higher speeds than larger devices. Currently, a single integrated circuit chip may contain over one billion patterns. Consequently, integrated circuit designs and semiconductor fabrication processes are extremely complex, since hundreds of processing steps may be involved. Occurrence of a mistake or small error at any of the design or process steps may necessitate redesign or cause lower yield in the final semiconductor product, where yield may be defined as the number of functional devices produced by the process as compared to the theoretical number of devices that could be produced assuming no bad devices.
Improving time-to-market and yield is a critical problem in the semiconductor manufacturing industry and has a direct economic impact on the semiconductor industry. In particular, a reduced time-to-market and higher yield translate into earlier availability and more devices that may be sold by the manufacturer.
Semiconductor integrated circuit (IC) design and manufacturing processes have become increasingly challenging with each new technology node. Classically, the communication of IC requirements between design and manufacturing has been enabled through a set of global and comprehensive design rules. However, with the emergence of sub-wavelength photolithography, the nonlinearity of the pattern transfer process onto semiconductor material such as silicon has increased dramatically. Due to this phenomenon, the effectiveness of the conventional IC design methodology has been significantly decreasing.
Considered in more detail, modern IC design layout data are becoming larger and larger with decreasing feature sizes and increasing complexity of physical layouts. With system on chip (SoC) design, a single IC design can contain multiple types of designs including SRAM, standard cells, random logic, analog, etc., which all have different physical characteristics and also different manufacturing requirements.
Known commercially available techniques for partition or extraction of an IC design layout include brute force division (rectangular mesh), as well as instance- or cell-based division. Clustering-based techniques as described in U.S. Published Patent Application 20020152454 or space-separation-based split techniques as described in U.S. Pat. No. 6,813,758 B1 are also known. However, as the design layout becomes more dense or a layout is compacted, the ability to apply conventional partitioning techniques, for example, to form clusters or achieve space separation, is becoming more difficult and frequently does not yield desirable layout data partitions.
On the other hand, IC design layouts require more and more post-design processing for enhanced manufacturability, typically in the form of resolution enhancement techniques (RET) including optical proximity correction (OPC), sub-resolution assist features (SRAF), and phase-shifting masks (PSM), as well as layout modifications including via doubling, wire spreading, and compaction. The increasing size and complexity of IC design layouts with the growing demand for post-design RET have created a bottleneck for transferring design to manufacturing with a fast product introduction and turn around. Due to the size of the IC design layout, the requirement for hardware and software, including software capacity, hardware memory, processing power, etc., is becoming more demanding.
As the feature size decreases, distortion in the pattern transfer process becomes more severe. The design shapes must be modified in order to print the desired images on the wafer. The modifications account for limitations in the optical lithography process. In the case of OPC, modifications of the design image account for optical limitations as well as mask fabrication limitations and resist limitations. Modifications of the design image can also account for the subsequent process steps like dry etching or implantation. It can also account for flare in the optical system, as well as pattern density variations. Another application of proximity effect correction is the compensation of the effects of aberrations of the optical system used to print the image of the mask onto the wafer. In this case, a mask with aberration correction would be dedicated to a given lithography tool as the aberrations are tool-specific.
FIG. 1 illustrates the modification of the mask data to correct for proximity effects. The processing of the mask data starts with a target layout 1 representing the desired dimensions of the image on the wafer. The printed image 2 of the target layout 1 differs from the desired image due to proximity effect. For reference, the target image 1 is shown with the printed image 2. The edges of the features are then moved (3) so that the corresponding printed image on the wafer 4 is correct (as close to the target as possible). In FIG. 1, all the areas of the layout have been corrected, but different degrees of proximity effect correction aggressiveness can be applied to different regions depending on the criticality of the region in the integrated circuit.
The corrections to layout 1 can be applied using a rule-based approach or a model-based approach. For a rule-based approach (rule-based OPC, or ROPC), the displacement of the segments would be set by a list of rules depending, for example, on the feature size and its environment. For a model-based approach (model-based OPC, or MOPC), the printed image on the wafer would be simulated using a model of the pattern transfer process. The correction would be set such that the simulated image matches the desired wafer image. A combination of rule-based OPC and model-based OPC, sometimes referred to as hybrid OPC, can also be used.
In the case of model-based OPC, the original layout 1 as shown in FIG. 2 is dissected in smaller segments 5 shown in modified layout 6. Each segment is associated with an evaluation point 7. The printed errors of the evaluation points are compensated by moving the corresponding segment in a direction perpendicular to the segment as shown in the final layout 8. The segments are corrected using multiple iterations in order to account for corrections of neighboring segments.
The image quality can be improved by adding printing or non-printing sub-resolution assist features along the edges of the main features. These assist features modify the diffraction spectrum of the pattern in a way that improves the printing of the main feature. The practical implementation of assist features is enhanced with the use of proximity effect correction as described above to correct for any optical printing artifact as well as resist and etch artifacts.
The image quality of an IC design layout can also be improved by another RET known as phase-shifting masks as described in U.S. Pat. No. 5,858,580, for example. In this case, at least two different regions are created on the masks corresponding to different phase and transmission of the light either going through these regions (for transparent mask) or reflected by these regions (for reflective mask). The phase difference between the two regions is chosen to be substantially equal to 180 degrees. The destructive interference between adjacent regions of opposite phase creates a very sharp contrast at the boundary between the regions, thus leading to the printing of small features on the wafer.
Two main classes of phase-shifting masks are currently in use. For the first class, the amount of light transmitted for transparent masks (or reflected for reflective masks) by one region is only a portion of the light transmitted (or reflected) by the other region, typically 5% to 15%. These masks are referred to as attenuated phase-shifting masks or half-tone phase-shifting masks. In some implementations of attenuated phase-shifting masks, some opaque regions (for transparent masks) or non-reflective regions (for reflective masks) are defined on the mask in order to block the light. This type of mask is referred to as a tri-tone mask. For the second class, the light transmitted (for transparent masks) or reflected (for reflective masks) by one region is substantially equal to the light transmitted (for transparent masks) or reflected (for reflective masks) by the other region. The second class of masks includes the following types of phase-shifting masks: alternating aperture phase-shifting masks, chromeless phase-shifting masks, and rim phase-shifting masks. The practical implementation of these techniques is improved with the use of proximity effect correction as described above to correct for any optical printing artifact as well as resist and etch artifacts. All the techniques can be combined with the use of assist features.
Meanwhile, since an IC design layout contains different designs which often require different RET settings and specifications, it is increasingly difficult for a single software tool to be able to accommodate different needs for different types of designs in the same layout. Today's RET tools including OPC, PSM, and design rule check (DRC) tools, for example, can typically be configured only to work globally for a whole layout, whereas the optimal solution may be to localize the layout and optimize settings individually.
Thus, for all these reasons, it would be desirable to provide an IC design layout system and method which overcome the above limitations and disadvantages of conventional systems and techniques and provide a layout partitioning or extraction tool that can split an IC design layout into somewhat independent portions so that they can each be processed independently and optimally to facilitate generation of IC design layouts having improved manufacturability. It is to this end that the present invention is directed. The various embodiments of the present invention provide many advantages over conventional IC design layout systems and techniques.